Portmapping for SRGs with multiple circuit packs

[transportpce.git] / common / src / main / java / org / opendaylight / transportpce / common / mapping / PortMappingVersion121.java

diff --git a/common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion121.java b/common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion121.java
index 7d605c717bacc3907893d2abcd6e8eb8bfa8aaf3..f2ec53a68924a07f25213481eebc35c58dd20920 100644 (file)
--- a/common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion121.java
+++ b/common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion121.java
@@ -295,12 +295,12 @@ public class PortMappingVersion121 {
         for (Entry<Integer, List<org.opendaylight.yang.gen.v1.http.org.openroadm.device.rev170206.srg.CircuitPacks>>
                 srgCpEntry : getSrgCps(nodeId, deviceInfo).entrySet()) {
             List<String> keys = new ArrayList<>();
+            int portIndex = 1;
             for (org.opendaylight.yang.gen.v1.http.org.openroadm.device.rev170206.srg.CircuitPacks
                     cp : srgCpEntry.getValue()) {
                 String circuitPackName = cp.getCircuitPackName();
                 List<Ports> portList = getPortList(circuitPackName, nodeId);
                 Collections.sort(portList, new SortPort121ByName());
-                int portIndex = 1;
                 for (Ports port : portList) {
                     if (!checkPortQual(port, circuitPackName, nodeId)) {
                         continue;