X-Git-Url: https://git.opendaylight.org/gerrit/gitweb?a=blobdiff_plain;f=tests%2Ftransportpce_tests%2F7.1%2Ftest01_portmapping.py;fp=tests%2Ftransportpce_tests%2F7.1%2Ftest01_portmapping.py;h=b297e77cff4970a24e0fdd1f29b8a858ffedf0df;hb=6233872e577c6abc704af61bc26362202017c103;hp=1f3f7791f3b1e548b9438ed997096f1b0dba3988;hpb=4c840d2a0863e5dc19a1b89c8da9bc64d58ca0e0;p=transportpce.git

diff --git a/tests/transportpce_tests/7.1/test01_portmapping.py b/tests/transportpce_tests/7.1/test01_portmapping.py
index 1f3f7791f..b297e77cf 100644
--- a/tests/transportpce_tests/7.1/test01_portmapping.py
+++ b/tests/transportpce_tests/7.1/test01_portmapping.py
@@ -143,18 +143,16 @@ class TransportPCE400GPortMappingTesting(unittest.TestCase):
         self.assertEqual('InService', res['mapping'][0]['port-admin-state'])
         self.assertEqual('InService', res['mapping'][0]['port-oper-state'])
         self.assertEqual('mpdr', res['mapping'][0]['xponder-type'])
-        self.assertEqual({
-            "min-trib-slot": "1.1",
-            "max-trib-slot": "1.20"
-        }, res['mapping'][0]['mpdr-restrictions'])
+        self.assertEqual(1.1, float(res['mapping'][0]['mpdr-restrictions']['min-trib-slot']))
+        self.assertEqual(1.2, float(res['mapping'][0]['mpdr-restrictions']['max-trib-slot']))
 
     # Added test to check mc-capability-profile for a transponder
     def test_08_check_mccapprofile(self):
         res = test_utils_rfc8040.get_portmapping_node_attr("XPDR-A2", "mc-capabilities", "XPDR-mcprofile")
         self.assertEqual(res['status_code'], requests.codes.ok)
         self.assertEqual(res['mc-capabilities'][0]['mc-node-name'], 'XPDR-mcprofile')
-        self.assertEqual(str(res['mc-capabilities'][0]['center-freq-granularity']), '3.125')
-        self.assertEqual(str(res['mc-capabilities'][0]['slot-width-granularity']), '6.25')
+        self.assertEqual(float(res['mc-capabilities'][0]['center-freq-granularity']), 3.125)
+        self.assertEqual(float(res['mc-capabilities'][0]['slot-width-granularity']), 6.25)
 
     def test_09_mpdr_switching_pool(self):
         response = test_utils_rfc8040.get_portmapping_node_attr("XPDR-A2", "switching-pool-lcp", "1")