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(parent: 0729c66) | patch
Fix bug in portmapping 74/95474/1
authorChristophe Betoule <christophe.betoule@orange.com>
Thu, 11 Mar 2021 15:59:42 +0000 (16:59 +0100)
committerGuillaume Lambert <guillaume.lambert@orange.com>
Mon, 29 Mar 2021 07:58:59 +0000 (07:58 +0000)
commit62d8105bc2929021ae287947bd6519080a93ac90
treedc19e53839ceb89e06e02ef368526743f52bc911tree | snapshot
parent0729c665aed798eaf1ab3776c3ab95add736c223commit | diff
Fix bug in portmapping

Sort the way circuit-packs are handling when creating mapping object in
order to have logical affectation of logical-connection-point and their
associated ports.

JIRA: TRNSPRTPCE-418
Signed-off-by: Christophe Betoule <christophe.betoule@orange.com>
Co-authored-by: Gilles Thouenon <gilles.thouenon@orange.com>
Change-Id: I92770308a1828229940e8d25ce6f1fc0f1f35917
(cherry picked from commit e38168def8a2fe710c6eb37cfe2f6bab7c9b0f4a)
common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion221.java diff | blob | history
common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion710.java diff | blob | history
Repository for Transport PCE project.