Fix a typo in Silicon planning 43/93043/1
authorRobert Varga <robert.varga@pantheon.tech>
Wed, 14 Oct 2020 09:58:57 +0000 (11:58 +0200)
committerRobert Varga <robert.varga@pantheon.tech>
Wed, 14 Oct 2020 09:58:57 +0000 (11:58 +0200)
commit80399fa2e83dbdff5a6af7f3dd10e1e2c5f96715
treec3a10f7f677dd0e8f82884af3d0ea630afb433a0
parentf710fb3ddc6e8cc38bde345b0addfc5aa81fa29c
Fix a typo in Silicon planning

We probably did not have this milestone done a year ago, let's try
to meet it this year.

Change-Id: Iac677ffa4df46f614f1efa29543ef6d7c051c0b3
Signed-off-by: Robert Varga <robert.varga@pantheon.tech>
docs/release-process/release-schedule.rst