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(parent: 93a79ca) | patch
Fix a typo in Silicon planning 61/92961/1
authorRobert Varga <robert.varga@pantheon.tech>
Wed, 14 Oct 2020 09:58:57 +0000 (11:58 +0200)
committerThanh Ha (zxiiro) <zxiiro@gmail.com>
Wed, 14 Oct 2020 16:05:48 +0000 (16:05 +0000)
commita58b4b59c01cc7e281df00ef7d5a8699790f90d2
tree662a94ccc9a4c483f3eac0cfebaf904710e883batree | snapshot
parent93a79ca2c3131ab6c5552ba9721fda8b35744759commit | diff
Fix a typo in Silicon planning

We probably did not have this milestone done a year ago, let's try
to meet it this year.

Change-Id: Iac677ffa4df46f614f1efa29543ef6d7c051c0b3
Signed-off-by: Robert Varga <robert.varga@pantheon.tech>
(cherry picked from commit 80399fa2e83dbdff5a6af7f3dd10e1e2c5f96715)
docs/release-process/release-schedule.rst diff | blob | history
OpenDaylight Documentation