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Updated git submodules
authorLuis Gomez <ecelgp@gmail.com>
Thu, 13 Oct 2016 20:19:43 +0000 (20:19 +0000)
committerGerrit Code Review <gerrit@opendaylight.org>
Thu, 13 Oct 2016 20:19:43 +0000 (20:19 +0000)
Project: releng/builder master cdd3c3e2a2b7267f547f136621867126712c50c6

Merge "Add RAM for dsbenchmark job"

Add RAM for dsbenchmark job

Change-Id: I203e058f57c31fe60c9435a53eafd7676f85f277
Signed-off-by: Vratko Polak <vrpolak@cisco.com>
docs/submodules/releng/builder patch | blob | history

diff --git a/docs/submodules/releng/builder b/docs/submodules/releng/builder
index e7b910fbfd96a70e8459e5adbc4b205d8e1a729c..cdd3c3e2a2b7267f547f136621867126712c50c6 160000 (submodule)
--- a/docs/submodules/releng/builder
+++ b/docs/submodules/releng/builder
@@ -1 +1 @@
-Subproject commit e7b910fbfd96a70e8459e5adbc4b205d8e1a729c
+Subproject commit cdd3c3e2a2b7267f547f136621867126712c50c6
OpenDaylight Documentation