Distinguish flex vs fixed for PCE 400G 10/96110/24
authorBalagangadhar Bathula <bb4341@att.com>
Mon, 10 May 2021 19:25:02 +0000 (15:25 -0400)
committerguillaume.lambert <guillaume.lambert@orange.com>
Thu, 24 Jun 2021 14:47:48 +0000 (16:47 +0200)
commita8d3b0cd1f14d5a12b8cb9a02ff882af4e86993c
treed09182b1ff603247885558a2c862d7221cf5f909
parentb972540ee7e5ed033f376019218cacebcd4e71b4
Distinguish flex vs fixed for PCE 400G

- PCE is not picking the flex vs fixed grid correctly
- Enable mc-capabilities for XPDR node type
- In addition to slot-width add central-frequency-granularity to
  distinguish fixed/flex grid.
- Add functional test to check mc-capability-profile on 7.1 XPDR device
- Add mc-capability profile in the operational data for XPDR-C1

JIRA: TRNSPRTPCE-452
Change-Id: I2c7adf862ccaeec4829a62faad56d94ad2616f38
Signed-off-by: Balagangadhar Bathula <bb4341@att.com>
15 files changed:
api/src/main/yang/transportpce-portmapping@2021-04-26.yang
common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion710.java
pce/src/main/java/org/opendaylight/transportpce/pce/graph/PostAlgoPathValidator.java
pce/src/main/java/org/opendaylight/transportpce/pce/networkanalyzer/PceCalculation.java
pce/src/main/java/org/opendaylight/transportpce/pce/networkanalyzer/PceNode.java
pce/src/main/java/org/opendaylight/transportpce/pce/networkanalyzer/PceOpticalNode.java
pce/src/main/java/org/opendaylight/transportpce/pce/networkanalyzer/PceOtnNode.java
pce/src/test/java/org/opendaylight/transportpce/pce/PcePathDescriptionTests.java
pce/src/test/java/org/opendaylight/transportpce/pce/constraints/PceConstraintsTest.java
pce/src/test/java/org/opendaylight/transportpce/pce/graph/PceGraphEdgeTest.java
pce/src/test/java/org/opendaylight/transportpce/pce/graph/PceGraphTest.java
pce/src/test/java/org/opendaylight/transportpce/pce/networkanalyzer/PceLinkTest.java
pce/src/test/java/org/opendaylight/transportpce/pce/networkanalyzer/PceOpticalNodeTest.java
tests/sample_configs/openroadm/7.1/oper-XPDRC.xml
tests/transportpce_tests/7.1/test_portmapping.py