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(parent: 007a7c5) | patch
Fix bug in portmapping 88/95488/4
authorChristophe Betoule <christophe.betoule@orange.com>
Thu, 11 Mar 2021 15:59:42 +0000 (16:59 +0100)
committerChristophe Betoule <christophe.betoule@orange.com>
Wed, 24 Mar 2021 14:18:09 +0000 (15:18 +0100)
commite38168def8a2fe710c6eb37cfe2f6bab7c9b0f4a
tree6568569028c103f25999baf8296ddc44464bb681tree | snapshot
parent007a7c53b32f289c795d1135c170a231ae4cbf67commit | diff
Fix bug in portmapping

Sort the way circuit-packs are handling when creating mapping object in
order to have logical affectation of logical-connection-point and their
associated ports.

JIRA: TRNSPRTPCE-418
Signed-off-by: Christophe Betoule <christophe.betoule@orange.com>
Co-authored-by: Gilles Thouenon <gilles.thouenon@orange.com>
Change-Id: I92770308a1828229940e8d25ce6f1fc0f1f35917
common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion221.java diff | blob | history
common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion710.java diff | blob | history
Repository for Transport PCE project.