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(parent: 0ccb06d) | patch
Portmapping for SRGs with multiple circuit packs 51/99551/3
authorJonas Mårtensson <jonas.martensson@ri.se>
Tue, 1 Feb 2022 17:44:53 +0000 (18:44 +0100)
committerJonas Mårtensson <jonas.martensson@ri.se>
Thu, 3 Feb 2022 13:40:05 +0000 (14:40 +0100)
commite95727123e625bf3966768a0201c8823fbc6c198
treed576c8cea191bbd0f748c37e4afe349b4daa8734tree | snapshot
parent0ccb06de76ba8b01ad1a6a25537d183a489f024dcommit | diff
Portmapping for SRGs with multiple circuit packs

The createPpPortMapping function was resetting the logical connection
port index to 1 for every new circuit pack in an SRG so that multiple
physical ports (cp-name/port-name) were mapped to the same logical PP
port.

Move "int portIndex = 1;" to before the loop over cicuit packs.

JIRA: TRNSPRTPCE-598
Signed-off-by: Jonas Mårtensson <jonas.martensson@ri.se>
Change-Id: Ifaf4353d3eca0ee76f7e46cc81084ff5110b85f3
common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion121.java diff | blob | history
common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion221.java diff | blob | history
common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion710.java diff | blob | history
Repository for Transport PCE project.