Distinguish flex vs fixed for PCE 400G 71/97071/1
authorBalagangadhar Bathula <bb4341@att.com>
Mon, 10 May 2021 19:25:02 +0000 (15:25 -0400)
committerBalagangadhar Bathula <bb4341@att.com>
Tue, 3 Aug 2021 16:56:38 +0000 (12:56 -0400)
commit5b9cf39548731ff65bafb0ed1c032931a5b9e758
treeb154df7659e7500ff73713e3a0d8cc671e0dfbb5
parentf6e2b6988193c96751895d4ae14fa80bf7cf7cd0
Distinguish flex vs fixed for PCE 400G

- PCE is not picking the flex vs fixed grid correctly
- Enable mc-capabilities for XPDR node type
- In addition to slot-width add central-frequency-granularity to
  distinguish fixed/flex grid.
- Add functional test to check mc-capability-profile on 7.1 XPDR device
- Add mc-capability profile in the operational data for XPDR-C1

JIRA: TRNSPRTPCE-452
Change-Id: I2c7adf862ccaeec4829a62faad56d94ad2616f38
Signed-off-by: Balagangadhar Bathula <bb4341@att.com>
15 files changed:
api/src/main/yang/transportpce-portmapping@2021-04-26.yang
common/src/main/java/org/opendaylight/transportpce/common/mapping/PortMappingVersion710.java
pce/src/main/java/org/opendaylight/transportpce/pce/graph/PostAlgoPathValidator.java
pce/src/main/java/org/opendaylight/transportpce/pce/networkanalyzer/PceCalculation.java
pce/src/main/java/org/opendaylight/transportpce/pce/networkanalyzer/PceNode.java
pce/src/main/java/org/opendaylight/transportpce/pce/networkanalyzer/PceOpticalNode.java
pce/src/main/java/org/opendaylight/transportpce/pce/networkanalyzer/PceOtnNode.java
pce/src/test/java/org/opendaylight/transportpce/pce/PcePathDescriptionTests.java
pce/src/test/java/org/opendaylight/transportpce/pce/constraints/PceConstraintsTest.java
pce/src/test/java/org/opendaylight/transportpce/pce/graph/PceGraphEdgeTest.java
pce/src/test/java/org/opendaylight/transportpce/pce/graph/PceGraphTest.java
pce/src/test/java/org/opendaylight/transportpce/pce/networkanalyzer/PceLinkTest.java
pce/src/test/java/org/opendaylight/transportpce/pce/networkanalyzer/PceOpticalNodeTest.java
tests/sample_configs/openroadm/7.1/oper-XPDRC.xml
tests/transportpce_tests/7.1/test_portmapping.py