Table Miss Verification Step

[integration/test.git] / csit / variables / netvirt / Variables.robot

diff --git a/csit/variables/netvirt/Variables.robot b/csit/variables/netvirt/Variables.robot
index b7c44c78bf18f910e198616edb79f50cad9023cf..d7efd8386503bdde6df6cc1e484ce9198cc9fedc 100644 (file)
--- a/csit/variables/netvirt/Variables.robot
+++ b/csit/variables/netvirt/Variables.robot
@@ -91,3 +91,8 @@ ${EGRESS_ACL_TABLE}    240
 ${VLAN_INTERFACE_INGRESS_TABLE}    0
 ${EGRESS_LPORT_DISPATCHER_TABLE}    220
 ${EGRESS_LEARN_ACL_FILTER_TABLE}    244
+@{DEFAULT_FLOW_TABLES}    18    19    20    22    23    24    43
+...               45    48    50    51    60    80    81
+...               90    210    211    212    213    214    215
+...               216    217    239    240    241    242    243
+...               244    245    246    247